In recent years, with an increasing number of servers, complexity related to operations has been enlarged and operation cost has become a problem.
As a technology to reduce the operation cost, server integration whereby a plurality of servers are integrated into a single server has attracted attention. As a technology of realizing server integration, the virtual machine technology that divides a single computer logically at arbitrary ratios is known. With the virtual machine technology, for example, firmware (or middleware), such as a hypervisor, divides a physical computer into a plurality of logical partitions (LPAR: Logical partition), allocates computer resources (a CPU, a main storage, and I/O) to each LPAR, and makes an OS work on each LPAR, respectively. Alternatively, a single host OS (OS that directly uses the physical machine) is executed on a single server, and a hypervisor that operates on this host OS performs the same division processing and makes a plurality of guest OS's (OS that operates on the host OS) perform operations.
In this way, the virtual machine technology enables OS's that operated on a plurality of servers conventionally and pieces of software that operated on the OS's to operate on a single server, realizing server integration. Although the virtual machine technology is a technology that has heretofore been used in large computers, such as main frames, it is spreading also with low-end servers and personal computers with improved performance of microprocessors in recent years. Incidentally, regarding the virtual machine technology, the following techniques are generally known.
For example, U.S. Pat. No. 6,907,600 describes a software technique of emulating a memory privileged instruction using an x86 compatible CPU. With this technique, a shadow page table (active translation data structure) is provided on a virtual machine monitor (hereinafter referred to as VMM), and a P-bit of this shadow page table is set to “0” in order to perform judgment of the necessity of emulation.
U.S. Pat. No. 6,996,748 shows a hardware function (Page Fault Error Code Mask/Match) in the virtual technology generally called VT-x (Virtualization Technology for x86). In recent years, the x86 compatible CPU tends to have added a function of supporting the VMM. The use of this Page Fault Error Code Mask/Match function improves efficiency of judgment of the necessity of emulation with respect to page exception.
U.S. Pat. No. 6,397,242 describes a software technique of realizing virtual software using the x86 compatible CPU. Specifically, it illustrates an emulation method of register privileged instructions/memory privileged instructions.
Intel(R)64 and IA-32 Architectures Software Developer's Manual describes a basic architecture of a CPU of Intel, and AMD64 Architecture Programmer's Manual describes a basic architecture of a CPU of AMD.